Отрывок: 3.2. Clock frequency vs. flip-flops number It is known that the number of used flip-flops increases with the increasing target frequency [7]. The maximum frequency is limited by the longest path data has to take in one clock cycle. To shorten the longest path Vivado HLS compiler inserts additional flip-flops, trying to reach target frequency specified by a programmer. Figure 3...
Название : | Gaussian filtering for FPGA based image processing with High-Level Synthesis tools |
Авторы/Редакторы : | Shipitko, O.S. Grigoryev, A.S. |
Ключевые слова : | FPGA High-level synthesis Image processing Gaussian filter |
Дата публикации : | 2018 |
Издательство : | Новая техника |
Библиографическое описание : | Shipitko O.S. Gaussian filtering for FPGA based image processing with High-Level Synthesis tools/Shipitko O.S., Grigoryev A.S.//Сборник трудов IV международной конференции и молодежной школы «Информационные технологии и нанотехнологии» (ИТНТ-2018) - Самара: Новая техника, 2018. - С. 2922-2927 |
Аннотация : | With the gradual improvement and uprising interest from the industry to High-Level Synthesis tools, like Vivado HLS form Xilinx, Field Programmable Gate Arrays are becoming an attractive option for accelerator architecture in image processing domain. However, an efficient high-level design still requires knowledge of hardware specifics. A great amount of image processing operations falls into a group of convolution-based operators - operators which result depends only on a particular pixel and its neighborhood and obtained by performing a convolution between a kernel and a part of an image. This paper investigates the impact of factors, such as kernel size, target frequency, convolution implementation specifics, floating-point vs. fixed-point filter kernel, on resulting register-transfer level design of convolution-based operators and FPGA resources utilization. The Gaussian filter was analyzed as an example of a convolution-based operator. It is shown experimentally that floating-point operators require a noticeably larger amount of resources, rather fixed-point once. Resulting clock frequency independence from kernel size is demonstrated as well as the number of used flip-flops grows with the increasing target clock frequency is investigated in this work. |
URI (Унифицированный идентификатор ресурса) : | http://repo.ssau.ru/handle/Informacionnye-tehnologii-i-nanotehnologii/Gaussian-filtering-for-FPGA-based-image-processing-with-HighLevel-Synthesis-tools-69075 |
Другие идентификаторы : | Dspace\SGAU\20180513\69075 |
Располагается в коллекциях: | Информационные технологии и нанотехнологии |
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paper_394.pdf | Основная статья | 1.76 MB | Adobe PDF | Просмотреть/Открыть |
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